BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 109)

PDI Description
Slave Controller – IP Core for Xilinx FPGAs III-97
OUTVALID
DATA
t
DATA_to _OUTVA LID
Output DATA
t
OUTVA LID
t
OE_EX T_to _DATA _inv alid
OE_EXT
WD_TRIG
t
WD_TRIG
t
DATA _to _WD_TRIG
t
output_event_delay
t
DATA _to _SY NC
SYNC0/1
Zero or High-Impedance
Figure 42: Digital Output timing
OUTVALID
t OUT_ENA_valid t OUT_ENA_invalid
t
OUTVALID
OUT_ENA
Figure 43: OUT_ENA timing