BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 22)

Overview
III-10 Slave Controller – IP Core for Xilinx FPGAs
1.8 Design flow
The design flow for creating an EtherCAT Slave Controller based on the EtherCAT IP Core is shown
in the following picture:
IP Core
installation (eval)
Synthesis
User logic
Vendor ID package License file (full)
FPGA configuration file
Download
utility
FPGA
Buy-out license /
Quantity-based license
(license agreement)
grants permission
Evaluation Development
Download
utility
MAC ID
Vendor
ID
bit-
stream
Application
specific ESC
sources
VHDL
Verilog
Schematic
Production
FPGA
FPGA
Download
utility
FPGA
encrypted
VHD
FPGA configuration file
bit-
stream
(timebomb)
FPGA
(timebomb)
IP Core
installation (full)
encrypted
VHDL
or
Customer
License file (eval)
MAC ID
or
Figure 3: Design flow