BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 116)

PDI Description
III-104 Slave Controller – IP Core for Xilinx FPGAs
Table 53: Read/Write timing diagram symbols
Symbol Comment
A15..A0 Address bits [15:0]
D0_7..D0_0
D1_7..D1_0 Data bits byte 0 [7:0]
Data bits byte 1 [7:0]
I0_7..I0_0
I1_7..I1_0
I2_7..I2_0 Interrupt request register 0x0220 [7:0]
Interrupt request register 0x0221 [7:0]
Interrupt request register 0x0222 [7:0]
C0_2..C0_0
C1_2..C1_0 Command 0 [2:0]
Command 1 [2:0] (3 byte addressing)
Status 0: last SPI access had errors
1: last SPI access was correct
BUSY OUT
Enable 0: No Busy output, tread is relevant
1: Busy output on SPI_DO (edge sensitive)
BUSY 0: SPI slave has finished reading first byte
1: SPI slave is busy reading first byte
SPI_DO (MISO)
SPI_DI (MOSI)
SPI_CLK*
t DI_setup t DI_hold
t
CLK_to_DO_valid
A
12
t
CLK_to_DO_invalid
I0
7
Figure 45: Basic SPI_DI/SPI_DO timing (*refer to timing diagram for relevant edges of SPI_CLK)