BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 136)

PDI Description
III-124 Slave Controller – IP Core for Xilinx FPGAs
10.5.4 Timing specifications
The AXI PDI accepts read and write accesses simultaneously. Nevertheless, the AXI PDI is internally
restricted to perform one access in a single clock cycle (either read or write). Simultaneous read and
write accesses are internally serialized to meet this requirement. The worst case timing increases in
this situation as indicated in the AXI timing characteristics. In other words, the internal bandwidth is
shared between read and write channel if both make accesses simultaneously. If only one channel is
used, it gets the full bandwidth.
Table 63: AXI timing characteristics
Parameter Min Max Comment
PRELIMINARY TIMING
D 8, 16, 32, or 64 AXI data bus width (in Bits)
N 1 31 AXI bus clock factor (if bus clock is
a multiple of 25 MHz)
t
Clk
x 15 40 ns AXI bus clock period
CLK_PDI_EXT
t
Read
t
Write
a) t
CLK
+D * 5 ns
+x
15
b) 3.5 * t
CLK
+D * 5 ns
+100 ns
+x
15
a) 40 ns
+D * 5 ns
+x
15
b) 3.5 * t
CLK
+D * 5 ns
+180 ns
+x
15
c) 40 ns
+D * 10 ns
+x
15
d) 3.5 * t
CLK
+D * 10 ns
+180 ns
+x
15
Aligned read/write access time
a) synchronous (N=1-31), read
only or write only
b) asynchronous, read only or write
only
c) synchronous (N=1-31),
simultaneous read and write
d) asynchronous, simultaneous
read and write
BW
int
25 Mbyte/s Internal PDI bandwidth limit for the
sum of read and write accesses
15 EtherCAT IP Core: time depends on synthesis results