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11 distributed clocks sync/latch signals, 1 signals, 2 timing specifications – BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k User Manual

Page 138: Distributed clocks sync/latch signals, Signals, Timing specifications, Table 64: distributed clocks signals, Figure 63: distributed clocks signals, Figure 64: latchsignal timing, Figure 65: syncsignal timing

11 distributed clocks sync/latch signals, 1 signals, 2 timing specifications | Distributed clocks sync/latch signals, Signals, Timing specifications, Table 64: distributed clocks signals, Figure 63: distributed clocks signals, Figure 64: latchsignal timing, Figure 65: syncsignal timing | BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k User Manual | Page 138 / 144 11 distributed clocks sync/latch signals, 1 signals, 2 timing specifications | Distributed clocks sync/latch signals, Signals, Timing specifications, Table 64: distributed clocks signals, Figure 63: distributed clocks signals, Figure 64: latchsignal timing, Figure 65: syncsignal timing | BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k User Manual | Page 138 / 144
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