Artesyn MVME6100 Single Board Computer Installation and Use (June 2014) - Manual (Page 75)

Functional Description
MVME6100 Single Board Computer Installation and Use (6806800D58H) 75
4.13 Real-Time Clock/NVRAM/Watchdog Timer
The real-time clock/NVRAM/watchdog timer is implemented using an integrated SGS-
Thompson M48T37V Timekeeper SRAM and Snaphat battery. The minimum M48T37V
watchdog timer time-out resolution is 62.5 msec (1/16s) and maximum time-out period is 124
seconds. The interface for the Timekeeper and SRAM is connected to the MV64360 device
controller bus on the MVME6100 board. Refer to the MV64360 Data Sheet, listed in
Appendix C,
Related Documentation , for additional information and programming details.
4.14 IDSEL Routing
PCI device configuration registers are accessed by using the IDSEL signal of each PCI agent to
an A/D signal as defined in version 2.2 of the PCI specification. IDSEL assignments to on-board
resources are specified in the MVME6100 Programmer’s Guide.
4.15 Reset Control Logic
The sources of reset on the MVME6100 are the following:
 Powerup
 Reset Switch
 NVRAM Watchdog Timer
 MV64360 Watchdog Timer
 VMEbus controller – Tsi148 ASIC
 System Control register bit
4.16 Debug Support
The MVME6100 provides JTAG/COP headers for debug capability for Processor as well as PCI0
bus use. These connectors are not populated as factory build configuration.