Artesyn MVME6100 Single Board Computer Installation and Use (June 2014) - Manual (Page 66)

Functional Description
MVME6100 Single Board Computer Installation and Use (6806800D58H) 66
4.5 L3 Cache
The MVME6100 external L3 cache is implemented using two 8Mb SDR SRAM devices. The L3
cache bus is 72-bits wide (64 bits of data and 8 bits of parity) and operates at 211 MHz. The L3
cache interface is implemented with an on-chip, 8-way, set-associative tag memory. The
external SRAMs are accessed through a dedicated L3 cache port that supports one bank of
SRAM. The L3 cache normally operates in copyback mode and supports system cache
coherency through snooping. Parity generation and checking may be disabled by
programming the L3CR register. Refer to the PowerPC Apollo Microprocessor Implementation
Definition Book IV listed in
Appendix C, Related Documentation .
4.6 System Controller
The MV64360 is an integrated system controller for high performance embedded control
applications. The following features of the MV64360 are supported by the MVME6100:
The MV64360 has a five-bus architecture comprised of:
 A 72-bit interface to the CPU bus (includes parity)
 A 72-bit interface to DDR SDRAM (double data rate-synchronous DRAM) with ECC
 A 32-bit interface to devices
 Two 64-bit PCI/PCI-X interfaces
In addition to the above, the MV64360 integrates:
 Three Gigabit Ethernet MACs (only two are used on the MVME6100)
 2Mb SRAM
 Interrupt controller
 Four general-purpose 32-bit timers/counters
 I
2
C interface
 Four channel independent DMA controller