Artesyn MVME6100 Single Board Computer Installation and Use (June 2014) - Manual (Page 67)

Functional Description
MVME6100 Single Board Computer Installation and Use (6806800D58H) 67
All of the above interfaces are connected through a cross bar fabric. The cross bar enables
concurrent transactions between units. For example, the cross bar can simultaneously control:
 A Gigabit Ethernet MAC fetching a descriptor from the integrated SRAM
 The CPU reading from the DRAM
 The DMA moving data from the device bus to the PCI bus
4.6.1 CPU Bus Interface
The CPU interface (master and slave) operates at 133 MHz and +2.5V signal levels using MPX
bus modes. The CPU bus has a 36-bit address and 64-bit data buses. The MV64360 supports up
to eight pipelined transactions per processor. There are 21 address windows supported in the
CPU interface:
 Four for SDRAM chip selects
 Five for device chip selects
 Five for the PCI_0 interface (four memory + one I/O)
 Five for the PCI_1 interface (four memory + one I/O)
 One for the MV64360 integrated SRAM
 One for the MV64360 internal registers space
Each window is defined by base and size registers and can decode up to 4GB space (except for
the integrated SRAM, which is fixed to 256KB). Refer to the MV64360 Data Sheet, listed in
Appendix C, Related Documentation , for additional information and programming details.
4.6.2 Memory Controller Interface
The MVME6100 supports two banks of DDR SDRAM using 256Mb/ 512Mb DDR SDRAM
devices on-board. 1Gb DDR non-stacked SDRAM devices may be used when available. 133
MHz operation should be used for all memory options. The SDRAM supports ECC and the
MV64360 supports single-bit and double-bit error detection and single-bit error correction of
all SDRAM reads and writes.