Artesyn Centellis 2000 Shelf Release 3.0 Installation and Use (May 2014) - Manual (Page 134)

Non-Field-Replaceable Units
Centellis 2000 Shelf Release 3.0 Installation and Use (6806800L99G) 134
The update channel is fully compliant to the PICMG 3.0 R3.0 Specification. Therefore, details are
not described within this chapter. For more information, see the PICMG 3.0 R3.0 Specification.
5.2.4 Synchronization Clock Interface
The complete synchronization clock interface is bussed between the user card and node slots.
It provides a set of clock buses to support applications that require the exchange of
synchronous timing information among multiple boards in a shelf. The synchronization clock
interface path is:
terminator – node slot 1 – user card slot 1 – user card slot 2 – node slot 2 – terminator.
The termination resistors are mounted on the backplane.
The synchronization clock interface is fully compliant to the PICMG 3.0 R3.0 Specification.
Therefore, details are not described within this chapter. For more information, see the PICMG
3.0 R3.0 Specification.
5.3 Alarm Panel
The alarm panel is located on the front of the shelf. It provides LEDs for the following alarm
states of the system:
The signaling is controlled by the system manager via commands via the MF106. The alarm
states are controlled by the system manager.
The alarm panel is fully compliant to the PICMG 3.0 R3.0 Specification.
5.4 Power Inlet
The power inlet is located on the rear of the shelf.
Alarm State LED Color
Minor AMBER
Major RED
Critical RED