Altera Stratix GX Transceiver - Manual (Page 71)

Altera Corporation 3–25
January 2005 Stratix GX Transceiver User Guide
Basic Mode
Figure 3–22. Example of a Multi-Transceiver Block Device to Transmitter Interface Clocking Scheme in Basic
Mode
When TX_CORECLK is not enabled, the Quartus II software automatically
routes the CORECLK_OUT signal to the write clock of the phase
compensation FIFO module using a global, regional, or fast regional
resource. In a multi transceiver block configuration, this routing can lead
to timing violations because the coreclk_out per transceiver block
cannot guarantee phase relationship. Therefore, the TX_CORECLK with a
common clock is recommended for synchronous transmission.
Transceiver Block 0
Transceiver Block 1
Transceiver Block 2
Transceiver Block 3
PLD Transmit Data
Clock Domain
coreclk_out[0]
tx_in_0[15..0]
tx_coreclk[0]
coreclk_out[1]
tx_in_1[15..0]
tx_coreclk[1]
coreclk_out[2]
tx_in_2[15..0]
tx_coreclk[2]
coreclk_out[3]
tx_in_3[15..0]
tx_coreclk[3]
Altera Gigabit Transceiver Block PLD