Reset module design (reset_mod.v), Altgxb instantiation (incr_bist.v) – Altera Stratix GX Transceiver User Manual

Page 217

Altera Corporation

8–13

January 2005

Stratix GX Transceiver User Guide

Stratix GX Built-In Self Test (BIST)

.coreclk_out(coreclk_out),

.rx_bistdone(rx_bistdone),

.rx_bisterr(rx_bisterr),

.rx_clkout(rx_clkout),

.tx_out(tx_out));

reset_mod reset_mod_inst(

.clk(inclk),

.reset(reset_wire));

endmodule

Reset Module Design (reset_mod.v)

module reset_mod(clk, reset);

input clk;

output reset;

reg [19:0] counter;

reg reset;

always @ (posedge clk)

counter = counter +1;

always @ (counter) begin

if ((counter >= 20'b11111111111111100000) &&

(counter <= 20'b11111111111111111111))

reset = 1'b1;

else

reset = 1'b0;

end

endmodule

altgxb Instantiation (Incr_BIST.v)

module Incr_BIST (

inclk,

rx_in,

rx_slpbk,

rxdigitalreset,

tx_out,

coreclk_out,

rx_clkout,

rx_bistdone,

rx_bisterr);