Altera Stratix GX Transceiver User Manual
Page 43

Altera Corporation
2–25
January 2005
Stratix GX Transceiver User Guide
Stratix GX Analog Description
Figure 2–17. MegaWizard Plug-In Manager - ALTGXB (Page 5 of 7) - Receiver (3)
–
Notes to
:
(1)
Optional input signal that forces the CRU to lock to the reference clock. This disables the auto switch- over mode
that switches the CRU to lock-to-data mode. If both rx_locktorefclk and rx_locktodata are asserted, then
rx_locktodata
takes precedence.
(2)
Optional input signal that forces the CRU to lock to the incoming data. If both rx_locktorefclk and
rx_locktodata
are asserted, rx_locktodata takes precedence.
(3)
Optional output signal that indicates when the CRU is locked to the incoming data stream. The lock indication is
based on the following conditions:
a. The CRU PLL is within the prescribed PPM frequency threshold setting (125 PPM, 250 PPM, 500 PPM, 1,000 PPM)
of the CRU reference clock.
b. The reference clock and CRU PLL output are phase matched (~ phases are within 0.08 UI).
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
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- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
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- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
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- Avalon Verification IP Suite (224 pages)
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- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
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- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
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- Parallel Flash Loader IP (57 pages)
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- RAM Initializer (36 pages)
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