Incremental mode verifier – Altera Stratix GX Transceiver User Manual
Page 210
8–6
Altera Corporation
Stratix GX Transceiver User Guide
January 2005
Pattern Verifier
Be sure you do not use the rx_apllreset signal because the re-training
process of the CRU might cause false errors. A reference design is
included in
Incremental Mode Verifier
In the incremental mode, the BIST generator transmits the data pattern in
the following sequence: K28.5 (comma), K27.7 (SOF), Data (00-FF
incremental), K28.0, K28.1, K28.2, K28.3, K28.4, K28.6, K28.7, K23.7, K30.7,
K29.7 (EOF), and repeat.
The sync pattern on the receiver word aligner must be set to a K28.5
pattern (10'b0011111010) for proper synchronization between the
generator and verifier. As in the PRBS verification mode, the
synchronization is handled by a built-in state machine, so control of the
rx_enacdet
signal is not required.
The BIST verifier waits for the word aligner to synchronize. After
synchronization, the BIST verifier checks for the following sequence:
K27.7 (SOF), Data (00-FF incremental), K28.0, K28.1, K28.2, K28.3, K28.4,
K28.6, K28.7, K23.7, K30.7, and K29.7 (EOF). If it does not see a K27.7
(SOF) within 31 patterns, the rx_errdetect and rx_bistdone signals
go high, and the verifier stops. The verifier checks for this sequence twice
before setting the rx_bistdone signal high. If any errors are detected
before the verifier finishes, the rx_errdetect and rx_bistdone
signals go high. Use the rxdigitalreset signal to restart the
incremental verification. Do not use the rx_apllreset signal because
the retraining process of the CRU might cause false errors. A reference
design is included in
.
shows which loopback modes are supported for each
verification mode.
Table 8–2. Verification Modes
Verification Mode
Comma
Loopback Modes
2
8
-1
16'b1000000011111111
(A1A2 mode)
Serial or parallel
2
10
-1
10'b111111111
(10-bit mode)
Serial or parallel
Incremental
10'b0011111010
(10-bit mode)
Serial or parallel or post
8B/10B parallel