Figure 5–27 – Altera Stratix GX Transceiver User Manual
Page 145
Altera Corporation
5–33
January 2005
Stratix GX Transceiver User Guide
XAUI Mode
For example, if a refclkb pin is required to feed a transmitter PLL using
an IQ line, the refclkb pin cannot be in transceiver block 1, because IQ2
only feeds the receiver PLLs.
Figure 5–27. IQ Line Connections for EP1SGX40G
PLD
Global
Clocks
IQ0
IQ1
IQ2
16
Transceiver Block 2
TX PLL
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
Global Clks, I/O Bus, Gen Routing
IQ2
/2
Transceiver Block 3
TX PLL
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
Global Clks, I/O Bus, Gen Routing
IQ2
/2
TX PLL
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
Global Clks, I/O Bus, Gen Routing
IQ2
Transceiver Block 0
/2
Transceiver Block 1
TX PLL
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
Global Clks, I/O Bus, Gen Routing
IQ2
/2
TX PLL
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
Global Clks, I/O Bus, Gen Routing
IQ2
Transceiver Block 4
/2
4
4
4
4
4
refclkb
refclkb
refclkb
refclkb
refclkb
4
Receiver
PLLs
4
Receiver
PLLs
4
Receiver
PLLs
4
Receiver
PLLs
4
Receiver
PLLs
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