Altera Stratix GX Transceiver User Manual
Page 245

Altera Corporation
9–19
January 2005
Stratix GX Transceiver User Guide
Reset Control & Power Down
Figure 9–6. Transmitter Reset Sequence
The waveform in
shows the functionality of the transmitter
, the pll_areset resets the entire transceiver block, including
both the analog and digital portions of the transmitter and receiver. After
this signal is deasserted, the controller waits until the transmitter PLL is
stable (pll_locked = 1'b1) before deasserting tx_digitalreset.
This ensures that the output of the transmitter PLL is stable before
releasing any of the logic that it feeds.
Start
pll_areset = high
txdigitalreset = high
pll_areset = low
txdigitalreset = high
pll_locked = high
pll_areset = low
txdigitalreset = low
transmit_digitalreset = high
pll_areset = low
txdigitalreset = high
YES
NO
YES
NO
async_reset or sync_reset
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
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