Altera Stratix GX Transceiver User Manual
Page 295

Altera Corporation
A–11
January 2005
Stratix GX Transceiver User Guide
D16.7
F0
111 10000
011011 0001
100100 1110
D17.7
F1
111 10001
100011 0111
100011 0001
D18.7
F2
111 10010
010011 0111
010011 0001
D19.7
F3
111 10011
110010 1110
110010 0001
D20.7
F4
111 10100
001011 0111
001011 0001
D21.7
F5
111 10101
101010 1110
101010 0001
D22.7
F6
111 10110
011010 1110
011010 0001
D23.7
F7
111 10111
111010 0001
000101 1110
D24.7
F8
111 11000
110011 0001
001100 1110
D25.7
F9
111 11001
100110 1110
100110 0001
D26.7
FA
111 11010
010110 1110
010110 0001
D27.7
FB
111 11011
110110 0001
001001 1110
D28.7
FC
111 11100
001110 1110
001110 0001
D29.7
FD
111 11101
101110 0001
010001 1110
D30.7
FE
111 11110
011110 0001
100001 1110
D31.7
FF
111 11111
101011 0001
010100 1110
Table A–2. Valid Data Code-Groups (Part 9 of 9)
Code-group Name
Octet Value
Octet Bits
HGF EDCBA
Current RD-
Current RD+
abcdei fghj
abcdei fghj
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)