Altera Stratix GX Transceiver - Manual (Page 273)

Altera Corporation 9–47
January 2005 Stratix GX Transceiver User Guide
Reset Control & Power Down
output rxdigitalreset;//GXB Receive digital reset
output rxanalogreset;//Receive power down signal
reg rxdigitalreset;
reg rxdigitalreset_rx_cruclk;
reg rxdigitalreset_rx_coreclk_Q;
reg rxanalogreset;
//Parameter value of T (2ms)based on the fastest clock (or 3.1875
Gbps)
parameter WAITSTATE_TIMER_VALUE = 1000000;
reg [19:0]waitstate_timer; //timer - for actual value, refer
stratix data sheet
//Receive Reset Sequence
always @(posedge rx_cruclk or posedge async_reset)
if(async_reset)
begin
rxanalogreset <= 1'b1;
rxdigitalreset_rx_cruclk <= 1'b1;
waitstate_timer <=
WAITSTATE_TIMER_VALUE;
end
else
begin
if(sync_reset)
begin
rxanalogreset <= 1'b1;
rxdigitalreset_rx_cruclk<= 1'b1;
waitstate_timer <=
WAITSTATE_TIMER_VALUE;
end
else
begin
rxanalogreset <= 1'b0;
if (rx_freqlocked)
begin
if(waitstate_timer == 0)
begin
waitstate_timer
<= waitstate_timer;
if(receive_digitalreset)
rxdigitalreset_rx_cruclk <= 1'b1;
else
rxdigitalreset_rx_cruclk <= 1'b0;
end
else