Altera Stratix GX Transceiver - Manual (Page 100)

4–18 Altera Corporation
Stratix GX Transceiver User Guide January 2005
SONET Mode Clocking
One of the clocking interfaces to consider while designing with Stratix GX
devices is the transceiver-to-FPGA interface. This clocking scheme is
further classified as the FPGA-to-transmitter channel and the
FPGA-to-receiver channel to the PLD.
In SONET mode, the read port of the transmitter phase compensation
FIFO module is either clocked by the coreclk_out or by the
tx_coreclk
signal. The constraint on using tx_coreclk is that the
clock must be frequency locked to the read clock of the transmitter phase
compensation FIFO module. Synchronous data transfers for a
multi-transceiver block configuration are accomplished by using the
tx_coreclk
port. The tx_coreclk of multi-transceiver blocks are
connected to a common clock domain either from a single coreclk_out
signal or from an FPGA system clock domain. This scheme is shown in
Figure 4–14 .