Altera Stratix GX Transceiver - Manual (Page 243)

Altera Corporation 9–17
January 2005 Stratix GX Transceiver User Guide
Reset Control & Power Down
pld clock domain(Generic name, can be any clock name) as read
clock. To reset the rx_clkout domain logic in
PLD fabric following reset is useful
*/
always @(posedge rx_clkout or posedge async_reset)
if(async_reset)
begin
rxdigitalreset_rx_clkout_Q <= 1'b1;
rxdigitalreset <= 1'b1;
end
else
begin
if(receive_digitalreset)
begin
rxdigitalreset_rx_clkout_Q <= 1'b1;
rxdigitalreset <= 1'b1;
end
else
begin
rxdigitalreset_rx_clkout_Q <=
rxdigitalreset_inclk;
rxdigitalreset <=
rxdigitalreset_rx_clkout_Q;
end
end
endmodule
Train Receive CRU With Transmit PLL Output Clock Option Disabled
The configuration in this section is similar to having two independent
transmit and receive PLLs with their respective input reference clocks
(inclk and rx_cruclk). In this configuration, both the transmit and
receive parts of the transceiver are used.
Figure 9–5 shows the possible
clock options for the selected transceiver configuration.