Altera Stratix GX Transceiver - Manual (Page 127)

Altera Corporation 5–15
January 2005 Stratix GX Transceiver User Guide
XAUI Mode
PCS - XGMII Code Conversion
In XAUI mode, the 8b/10b decoder in Stratix GX transceivers is
controlled by a global receiver state machine that maps various PCS
code-groups into specific 8-bit XGMII codes.
Table 5–3 lists the PCS code
group to XGMII character mapping.
Byte Deserializer
The byte deserializer module reduces the speed at which the FPGA logic
array must run to meet performance specifications. It is possible to bring
the data rate down from the line rate by a factor of 20.
The input to this module is 8 bits of data; the output to the FPGA logic
array is deserialized to 16 bits. The byte deserializer does not process the
data, and therefore, the control signals fed to the module are simply
processed to match the latency to the data.
The byte deserializer in the receiver block takes in up to 13 bits. It is
possible to feed the following to the byte deserialzer:
■ 8 bits of data and up to 2 control signals (rx_patterndetect,
rx_syncstatus
)
■ 8 bits of data and up to 5 control signals (rx_patterndetect,
rx_syncstatus
, rx_disperr, rx_ctrldetect, and
rx_errdetect )
Table 5–3. PCS Code-Group to XGMII Character Mapping Note (1)
XGMII RXC XGMII RXD PCS Code Group Description
0 00 through FF Dxx.y Normal data
reception
1 07 K28.0 or K28.3 or
K28.5
Idle in ||I||
1 07 K28.5 Idle in ||T||
1 9C K28.4 Sequence
1 FB K27.7 Start
1 FD K29.7 Terminate
1 FE K30.7 Error
1 FE Invalid code-group Received code-
group
Note to Table 5–3 :
(1) Values in RXD column are in hexadecimal.