Altera Stratix GX Transceiver - Manual (Page 137)

Altera Corporation 5–25
January 2005 Stratix GX Transceiver User Guide
XAUI Mode
Figure 5–21. Default Configuration of altgxb Megafunction in XAUI Mode
You can disable the train receiver PLL CRU clock from transmitter PLL
feature in the altgxb MegaWizard
Plug-In. Deselecting this option
enables an additional rx_cruclk input reference clock port for the
receiver PLL. You can use this feature to support additional
multiplication factors for the receiver PLL, because it supports the
separation of receiver and transmitter reference clocks. This separation is
necessary if the output reference clock frequency from the transmitter
PLL exceeds the 325 MHz phase frequency detector of the receiver PLL
(see
Chapter 2, Stratix GX Analog Description for more information).
This configuration is shown in Figure 5–22 .
f
Refer to the Stratix GX FPGA Family data sheet for information on
parallel interface speeds for other device speed grades.