Xaui mode – Altera Stratix GX Transceiver User Manual
Page 15
Altera Corporation
1–7
January 2005
Stratix GX Transceiver User Guide
Introduction
Figure 1–3. Block Diagram of a Duplex Channel Configured in SONET Mode
XAUI Mode
Stratix GX transceivers contain embedded macros dedicated to
supporting the XAUI protocol, specified in clause 47 of the IEEE 802.3ae
specification. These macros includes synchronization, channel deskew,
rate matching, XGXS to XGMII, and XGMII to XGXS code-group
conversion. Refer to the XAUI Mode chapter for more details on the
configurability of this mode.
shows a block diagram of a
duplex channel configured in XAUI mode.
Deserializer
Serializer
Word
Aligner
8B/10B
Decoder
Channel
Aligner
Byte
Deserializer
8B/10B
Encoder
Phase
Compensation
FIFO Buffer
Reference
Clock
Reference
Clock
Byte
Serializer
Phase
Compensation
FIFO Buffer
Rate
Matcher
Digital Section
Analog Section
Receiver
PLL
Transmitter
PLL
Clock
Recovery
Unit
Receiver
Transmitter
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)