Altera External Memory PHY Interface - Manual (Page 65)

Chapter 3: Functional Description—ALTMEMPHY (nonAFI) 3–49
Design Considerations
© January 2010 Altera Corporation External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
Handshake Mechanism Between Write Commands and Write Data
Figure 3–15 shows the write operation for the full-rate controller. The handshake
mechanism remains similar to the half-rate controller except for the following
differences:
1. 1T versus 2T addressing.
As the burst size is fixed at four on the memory interface, and also the address and
command datapath is based on 1T addressing, it takes two memory clock cycles to
write data into the memory for each of the write commands, see
Figure 3–15 . The
first memory cycle is the write command and the second memory cycle is the NOP
command. Because of this arrangement, you see a NOP command between the
write commands.
2. Assertion of the chip select signal.
The chip select signal is asserted along with the write command because of the 1T
addressing.
3. To support full-rate, the controller must provide the ctl_mem_dqs_burst signal.
In full-rate mode, the PHY allows separates control of the DQ and DQS output
enables to support incomplete bursts. For example, if the memory burst length is
four and the local side burst length is two, you may ask for a write of length one.
To support this, the controller must be able to enable the DQS outputs for the full
memory burst length (two clock cycles, four DQS edges) while only enabling the
DQ outputs for the number of cycles that you requested (one clock cycle, two beats
of data).