Altera External Memory PHY Interface User Manual
Page 60
3–44
Chapter 3: Functional Description—ALTMEMPHY (nonAFI)
Design Considerations
External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
© January 2010
Altera Corporation
Some of the address and command signals generated by the controller are:
■
ctl_mem_addr_h
■
ctl_mem_cas_h
■
ctl_mem_cs_n_h
■
ctl_mem_ras_n_h
■
ctl_mem_we_n_h
■
ctl_mem_odt_h
shows the No Operation (NOP) command followed by a series of five
read commands.
1. The controller issues five consecutive read commands with a starting address of
0×0 with increments of four (0000, 0004, 0008, 000c, 0010), see the top of
under the PHY Command Input label.
2. The ALTMEMPHY megafunction generates the read command at the memory
interface after five-to-seven memory clock (mem_clk) cycles. The address and
commands are generated using the negative edge of the memory clock, see
under the PHY Command Output label.
3. The address and commands are of 2T period and the chip select is of 1T period
(mem_clk).
4. The data (mem_dq) at the memory interface is presented after three memory clock
cycles of read latency. The read latency is equal to the CAS latency. For this
example, CAS latency is equal to three.
By default, the read data from the memory bypasses the controller and is sent directly
to the user logic. If your controller requires access to the read data after it has been
captured, but before it is sent to the user interface (for example, to perform error
detection and correction), connect the ctl_mem_rdata and
ctl_mem_rdata_valid
outputs from the ALTMEMPHY megafunction to your
controller. The controller must delay both ctl_mem_rdata and
ctl_mem_rdata_valid
signals by the same amount. Connect the read data and
valid outputs of your controller to the ctl_rdata and ctl_rdata_valid inputs of
the ALTMEMPHY megafunction, which passes straight through to the local_rdata
and local_rdata_valid signals.
Handshake Mechanism Between Write Commands and Write Data
The controller provides a signal (ctl_mem_wdata_valid) to the ALTMEMPHY
megafunction to tell it when to enable the mem_dq and mem_dqs output enables. It is
the controller’s responsibility to control the relative timing of the memory command
signals (for example, mem_cas_n and mem_we_n) and the
control_mem_wdata_valid or control_mem_dqs_burst
signals, to meet the
required memory write latency; therefore, this exact relationship is very important.
1
The ctl_mem_dqs_burst signal controls the DQS output enables of the DQS pins.