Altera External Memory PHY Interface - Manual (Page 41)

Chapter 3: Functional Description—ALTMEMPHY (nonAFI) 3–25
Understanding the Testbench
© January 2010 Altera Corporation External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
Understanding the Testbench
Before the user logic (example driver) can read or write to the local interface, the
external SDRAM must first be initialized and calibrated. Following power-up or a
reset event, the following stages of operation take place:
■ PLL initialization and lock
■ Memory device initialization
■ Interface training and calibration
■ Write training data
■ Calibration
■ Functional memory use
PLL Initialization and Lock
PLL initialization and lock is the first activity that takes place and completes when the
signal pll_locked is first asserted. Typically this stage requires approximately
150 ns, but can take longer if the PLL Option Hold ‘locked’ output low for entered number> cycles after the PLL initializes is turned on.
The exact length of time required for pll_locked to become asserted depends on
several factors including Device Type, PLL Type, and PLL Configuration.
1
pll_locked is not included in the simulation default waveform view, and must be
added manually.
f For more information, refer to Phase-Locked Loop (ALTPLL) Megafunction User Guide .
Memory Device Initialization
Memory devices must be initialized before functional use. The exact sequence is
different for DDR2 and DDR SDRAM. The memory controller sets the operating
parameters of the memory based on the parameters you specify in the MegaWizard
interface. This parameter is fixed at generation time and is not dynamically editable
via the local interface.
Interface Training and Calibration
The sequencer element of the ALTMEMPHY megafunction performs path-delay
analysis to correctly set up the resynchronization (DQS mode devices), capture (Non
DQS Mode devices
) clocks and the data alignment settings. The sequencer issues
read and write commands to the memory controller over the ctl_* interface for DDR
and DDR2 SDRAM high-performance memory controllers, which is performed in the
following two stages:
■ Write training data
■ Calibration