Initialization stage, Initialization stage –29 – Altera External Memory PHY Interface User Manual
Page 45
Chapter 3: Functional Description—ALTMEMPHY (nonAFI)
3–29
Functional Simulation—the ModelSim Wave and Transcript Window
© January 2010
Altera Corporation
External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
Initialization Stage
The full window stage shows that the Memory initialization stage is dominated by the
NOP command where t
INIT
is 200 µs.
The exact sequence of commands differs between the various external memory
families (refer to the respective the device datasheets for further information). For this
DDR2 SDRAM example, the following sequence applies:
1. Issue NOP commands for 200 µs, programmable via t
INIT
parameter.
2. Assert mem_cke (high).
3. Issue a PCH, then wait for 400 ns after t
INIT
(400 ns is derived from dividing t
INIT
counter by 500).
4. Issue an LMR command to ELMR register 2 = 0.
5. Issue an LMR command to ELMR register 3 = 0.
6. Issue an LMR command to ELMR register to enable the memory DLL and set
Drive strength, AL, RTT, DQS#, RDQS, OE.
7. Issue an LMR command to MR register to reset DLL and set operating parameters.
8. Issue a PCH.
9. Issue an ARF.
10. Issue another ARF.
11. Issue an LMR command to MR register to set operating parameters.
12. Issue an LMR command to ELMR register to set default OCD and parameters. 200
clock cycles after DLL reset, the memory is initialized.
See
for the expected waveform view of the initialization
phase directly following the NOP of 200 µs. Steps
to
are expanded to increase
detail. Initialization is complete by the second yellow cursor. Additional signals are
added to simplify debugging.