Altera Phase-Locked Loop Reconfiguration IP Core User Manual
Page 51

Document Revision History
Page 51
Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction
February 2012
Altera Corporation
November 2007
3.2
■
Updated for the Quartus II software version 7.2, including: Added new user-mode
reconfiguration from external ROM.
■
Added three new input ports: rom_data_in, write_from_rom, and reset_rom_address
■
Added two new output ports: rom_address_out and write_rom_ena
■
Updated design example format
■
Updated:
,
,
,
,
,
■
Changed altpll_reconfig to ALTPLL_RECONFIG throughout the document.
March 2007
3.1
Added Cyclone III to list of supported devices.
December 2006
3.0
Updated for Quartus II software version 6.1.
October 2006
2.0
Updated for Quartus II software version 6.0.
April 2005
1.0
Initial release.
Table 15. Document Revision History (Part 2 of 2)
Date
Version
Changes
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- DCFIFO (28 pages)