Altera Phase-Locked Loop Reconfiguration IP Core - Manual (Page 15)

Design Example Page 15
Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation
Pulse Width Variation
This design example uses the ALTPLL_RECONFIG megafunction to modify the pulse
width of an enhanced PLL. This example demonstrates how to reconfigure the
c1
counter using the ALTPLL_RECONFIG megafunction to vary the pulse width of this
counter by changing the high-count and low-count values. The formula for changing
the duty cycle is shown in
Figure 12 .
In this example, the pulse width is programmed to change from 50% to 25% , and then
to 75% of the duty cycle.
Generating the ALTPLL and ALTPLL_RECONFIG Megafunctions
To generate the ALTPLL and ALTPLL_RECONFIG megafunctions, perform the
following steps:
1. Open ALTPLL_RECONFIG_DesignExample_ex2.zip and extract
pll_recon_ex2_1.1.qar .
2. In the Quartus II software, open pll_recon_ex2_1.1.qar and restore the archive file
into your working directory.
3. On the Tools menu, click MegaWizard Plug-In Manager. Page 1 of the
MegaWizard Plug-In Manager appears.
4. Select Create a new custom megafunction variation.
5. Click Next. Page 2a of the MegaWizard Plug-In Manager appears.
Figure 12. Changing the Duty Cycle Formula
Duty cycle = (Ch/Ct) % high time count and (Cl/Ct) % low time count
with RSELODD = 0
Where:
Ch = High time count
Cl = Low time count
Ct = Total time
When you set RSELODD = 1, you subtract 0.5 cycles from the high time and
you add 0.5 cycles to the low time.
For example, if:
Ch = 2 cycles
Cl = 1 cycle
(Note: For odd division factors, the larger number is for the
Ch counter; the smaller number is for the CI counter.)
Setting RSELODD = 1 effectively changes the Ch and Cl to:
High time count = 1.5 cycles
Low time count = 1.5 cycles
Duty cycle = (1.5/3) % high time count and (1.5/3) % low time count