Altera Phase-Locked Loop Reconfiguration IP Core - Manual (Page 26)

Page 26 Design Example
Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation
Compiling the ALTPLL and ALTPLL_RECONFIG Megafunctions
To add the ALTPLL megafunction to the ALTPLL_RECONFIG megafunction, and
then compile the design in the Quartus II software, follow these steps:
1. On the Project menu, click Add/Remove Files in Project. The Settings dialog box
appears.
2. In the Category list, select Files.
3. Click Browse (...)
after File name and from the project folder, select
ALTPLL_RECONFIG_rom.v . This file is the top-level module that contains the
port-mapping between the pll_reconfig_circuit and the_pll instances.
4. To add the top-level file to the project, click Add.
5. Click OK.
6. On the File menu, click Save Project.
The top-level file is added to the project.
7. To compile the design, on the Processing menu, click Start Compilation.
8. When the Full Compilation was successful
message box appears, click OK.
You have now created and compiled the complete design file, which can be viewed in
the RTL Viewer (
Figure 20 ). To display the RTL Viewer, in the Tools menu, select
Netlist Viewers , and click on RTL Viewer.
This design consists of eight modules, which are:
1. the_pll:u1—This represents the Stratix III PLL (Top and Bottom PLL) that is to be
reconfigured. The settings are as follows:
■ inclk = 50 MHz
■ c0 = 100 MHz
Figure 20. Top-Level Design Implementation Using the RTL Viewer