Altera Phase-Locked Loop Reconfiguration IP Core - Manual (Page 38)

Page 38 Specifications
Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation
parameteruse_scanclk_sync_register = "NO",
parameterlpm_type = "altpll_reconfig",
parameterlpm_hint = "unused")
( outputwirebusy,
inputwireclock,
inputwire[2:0]counter_param,
inputwire[3:0]counter_type,
inputwire[8:0]data_in,
outputwire[8:0]data_out,
outputwirepll_areset,
inputwirepll_areset_in,
outputwirepll_configupdate,
outputwirepll_scanaclr,
outputwirepll_scanclk,
outputwirepll_scanclkena,
outputwirepll_scandata,
inputwirepll_scandataout,
inputwirepll_scandone,
outputwirepll_scanread,
outputwirepll_scanwrite,
inputwireread_param,
inputwirereconfig,
inputwirereset,
inputwirereset_rom_address,
outputwire[7:0]rom_address_out,
inputwirerom_data_in,
inputwirewrite_from_rom,
inputwirewrite_param,
outputwirewrite_rom_ena)/* synthesis syn_black_box=1 */;
endmodule //altpll_reconfig
VHDL Component Declaration
The following VHDL component declaration is located in the VHDL Design File
(.vhd) altera_mf_components.vhd in the directory>\libraries\vhdl\altera_mf directory.
component altpll_reconfig
generic (
intended_device_family:string := "unused";
init_from_rom:string := "NO";
pll_type:string := "UNUSED";