Kontron SMARC-sA3874i - Manual (Page 32)

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User’s Guide
The following table details the TI AM3874 to Atheros GBE Phy (AR8031) connection details.
TI Cortex A8 CPU Atheros AR8031 Net Name Notes
Pin # Pin Name Pin # Pin Name
G28 RGMII0_TXD0 36 TXD0 RGMII0_TXD[0] GBE controller RGMII transmit
data
G27 RGMII0_TXD1 37 TXD1 RGMII0_TXD[1]
F28 RGMII0_TXD2 38 TXD2 RGMII0_TXD[2]
H26 RGMII0_TXD3 39 TXD3 RGMII0_TXD[3]
J26 RGMII0_TXCTL 34 TXEN RGMII0_TXCTL RGMII transmit enable
H27 RGMII0_TXC 35 GTX_CLK RGMII0_TXC RGMII transmit clock
P23 RGMII0_RXD0 31 RXD0 RGMII0_RXD[0] GBE controller RGMII receive data
R23 RGMII0_RXD1 30 RXD1 RGMII0_RXD[1]
R25 RGMIIO_RXD2 28 RXD2 RGMII0_RXD[2]
T23 RGMII0_RXD3 27 RXD3 RGMII0_RXD[3]
L23 RGMII0_RXCTL 32 RX_DV RGMII0_RXCTL RGMII receive data valid signal
L24 RGMII0_RXC 33 RX_CLK RGMII0_RXC RGMII receive clock output
J27 EMAC_RMREFCLK/TI
M2_IO/GP1[10] 5 INT INT_ETH Interrupt signal to system
H28 MDCLK 1 MDC MDCLK Management data clock reference
P24 MDIO 48 MDIO MDIO Management data