Kontron SMARC-sA3874i - Manual (Page 17)

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User’s Guide
3.2.8 Parallel LCD Display Interface
The Sitara ARM CPU parallel 24 bit LCD interface is brought to the Module edge connector. The interface runs at
the 1.8V Module I/O voltage. This voltage swing may be used directly with 1.8V capable Carrier Board LVDS
transmitters, such as the TI SN75LVDS83B. The 1.8V signaling may not be suitable for direct connection to a
parallel flat panel. Generally speaking, only small panels, with screen diagonals of 5” or less, are available with a
1.8V interface. Larger parallel LCD panels are likely to use 3.3V signaling and a set of voltage translators / buffers
would be needed on the Carrier.
Figure 3: Sitara Module Parallel LCD Implementation
The mapping of the Sitara CPU parallel LCD balls to the ULP-COM edge connector is shown in the table below. For
24 bit implementations, all bits are used. For 18 bit implementations, in ULP-COM, the least significant bits (Red
D17:16, Green D9:8, Blue D1:0) are dropped.
E
D
G
E
F
IN
G
E
R
(J
3
)
SITARA CPU
(U7) VOUT0_HSYNC
VOUT0_VSYNC
VOUT0_CLK
AC11
AB13
AD12
RED
GREEN
BLUE
S120
S122
S121
S123
VOUT0_G[0:7]
VOUT0_R[0:7]
VOUT0_B[0:7]
CPLD
(U20)
B10
A10
B11
C10
LCD_DUAL_PCK
S142
LCD_DE
K9