Kontron SMARC-sA3874i - Manual (Page 15)

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User’s Guide
The following table details exactly how the Sitara ARM CPU parallel LCD pins are mapped to the on-Module Texas
Instruments SN65LVDS93AZ LVDS transmitter. For 18 bit displays, LVDS channels 0, 1 and 2 are used. For 24 bit
displays (that accept 18 bit color packing), channels 0, 1, 2 and 3 are used.
Sitara ARM Cortex CPU
LVDS Transmitter
(TI
SN65LVDS93AZ)
Net names
LV
DS
C
ha
nn
el
Tra
ns
mit Bi
t
Or
de
r
18 Bit
standard
Color
mapping
24 Bit/18
bit
compatible
Color
mapping
Pin # Pin Name Pin # Pin Name
AB8 VOUT[0]_G_Y_YC[4] K5 D7 VOUT0_G[2]
0
1 G0 G2
AC13 VOUT[0]_R_CR[9] J4 D6 VOUT0_R[7] 2 R5 R7
AE8 VOUT[0]_R_CR[8] K3 D4 VOUT0_R[6] 3 R4 R6
AF12 VOUT[0]_R_CR[7] J3 D3 VOUT0_R[5] 4 R3 R5
AF6 VOUT[0]_R_CR[6] K2 D2 VOUT0_R[4] 5 R2 R4
AF8 VOUT[0]_R_CR[5] K1 D1 VOUT0_R[3] 6 R1 R3
AA9 VOUT[0]_R_CR[4] J2 D0 VOUT0_R[2] 7 R0 R2
AD15 VOUT[0]_B_CB_C[5] D5 D18 VOUT0_B[3]
1
1 B1 B3
AD11 VOUT[0]_B_CB_C[4] E5 D15 VOUT0_B[2] 2 B0 B2
AF14 VOUT[0]_G_Y_YC[9] F6 D14 VOUT0_G[7] 3 G5 G7
AE14 VOUT[0]_G_Y_YC[8] G6 D13 VOUT0_G[6] 4 G4 G6
AD14 VOUT[0]_G_Y_YC[7] G5 D12 VOUT0_G[5] 5 G3 G5
AA8 VOUT[0]_G_Y_YC[6] J6 D9 VOUT0_G[4] 6 G2 G4
AB12 VOUT[0]_G_Y_YC[5] K6 D8 VOUT0_G[3] 7 G1 G3
AA10
VOUT[0]_AVID/VOUT
[0]_FLD
A3 D26 VOUT0_AVID
2
1 DE DE
AB13 VOUT[0]_VSYNC B4 D25 VOUT0_VSYNC 2 VS VS
AC11 VOUT[0]_HSYNC A4 D24 VOUT0_HSYNC 3 HS HS
AG15 VOUT[0]_B_CB_C[9] A6 D22 VOUT0_B[7] 4 B5 B7
AF15 VOUT[0]_B_CB_C[8] B5 D21 VOUT0_B[6] 5 B4 B6
AB10 VOUT[0]_B_CB_C[7] B6 D20 VOUT0_B[5] 6 B3 B5