Kontron SMARC-sA3874i User Manual
Page 27
27
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User’s Guide
E
D
G
E
F
IN
G
E
R
(J
3
)
CPLD
(U20)
SITARA
CPU
(U7)
P62
P67
F3
G1
L5
K5
AE27
AF28
USB0_EN_OC#
USB1_OC#
USB0_OC#
USB1_EN_OC#
1
0
K
USB1_EN_OC_PU
USB0_EN_OC_PU
K10
F1
1
0
K
1v8 to 3v3
Translator
EN_USB0_VBUS_1V8
EN_USB1_VBUS_1V8
EN_USB0_VBUS_3V3
EN_USB1_VBUS_3V3
B1
C1
L5
AF11
3v3 to 1v8
Translator
USB0_OC_3V3#
USB1_OC_3V3#
Figure 4: External USB Port Power Distribution Logic Implementation
USB port power enable and over current logic implementation between the TI AM3874CPU and CPLD is shown in
the table below:
TI Cortex A8 CPU
CPLD
Net Name
Notes
Pin #
Pin Name
Pin #
Pin Name
AF11
USB0_DRVVBUS C1
IO_C1
EN_USB0_VBUS_1V8/
EN_USB0_VBUS_3V3
USB Port0 power enable
L5
USB1_DRVVBUS B1
IO_B1
EN_USB1_VBUS_1V8/
EN_USB1_VBUS_3V3
USB Port1 power enable
AE27
GMI_AD09
K5
IO_K5
USB0_OC#/
USB0_OC_3V3
USB Port0 over current indication
signal
AF28
GMI_CS1#
L5
IO_L5
USB1_OC#/
USB1_OC_3V3
USB Port1 over current indication
signal
USB port power-enable and over-current logic implementation between the CPLD and ULP-COM sA3874i edge
connector is shown in the table below:
CPLD
ULP-COM sA3874i
Edge Finger
Net Name
Notes
Pin #
Pin Name
Pin #
Pin Name
F3
IO_F3
P62
USB0_EN_
OC#
USB0_EN_OC#
USB Port0 power enable/over current
indication signal
G1
IO_G1
P67
USB1_EN_
OC#
USB1_EN_OC#
USB Port1 power enable/over current
indication signal