Achronix Speedster22i 10G/40G/100G Ethernet User Manual
Page 84
84
UG029, September 6, 2013
53
D4
MULTI-LANE
ALIGN
STATUS 4
RO
15:12: Reserved
11: Lane 19 alignment marker lock
10: Lane 18 alignment marker lock
9: Lane 17 alignment marker lock
8: Lane 16 alignment marker lock
7: Lane 15 alignment marker lock
6: Lane 14 alignment marker lock
5: Lane 13 alignment marker lock
4: Lane 12 alignment marker lock
3: Lane 11 alignment marker lock
2: Lane 10 alignment marker lock
1: Lane 9 alignment marker lock
0: Lane 8 alignment marker lock
Note: Bits 11:0 are reserved for 40GBASE-R.
0
54 -
89
D8 -
164
Reserved
0
90
168
BIP ERR
CNT
LANE 0
ROR
15:0: BIP error counter lane 0 (NR)
0
91
16C
BIP ERR
CNT
LANE 1
ROR
15:0: BIP error counter lane 1 (NR)
0
92
170
BIP ERR
CNT
LANE 2
ROR
15:0: BIP error counter lane 2 (NR)
0
93
174
BIP ERR
CNT
LANE 3
ROR
15:0: BIP error counter lane 3 (NR)
0
94
178
BIP ERR
CNT
LANE 4
ROR
15:0: BIP error counter lane 4 (NR)
Note: Bits 15:0 are reserved for 40GBASE-R.
0
95
17C
BIP ERR
CNT
LANE 5
ROR
15:0: BIP error counter lane 5 (NR)
Note: Bits 15:0 are reserved for 40GBASE-R.
0
96
180
BIP ERR
CNT
LANE 6
ROR
15:0: BIP error counter lane 6 (NR)
Note: Bits 15:0 are reserved for 40GBASE-R.
0
97
184
BIP ERR
CNT
LANE 7
ROR
15:0: BIP error counter lane 7 (NR)
Note: Bits 15:0 are reserved for 40GBASE-R.
0
98
188
BIP ERR
CNT
LANE 8
ROR
15:0: BIP error counter lane 8 (NR)
Note: Bits 15:0 are reserved for 40GBASE-R.
0
99
18C
BIP ERR
CNT
LANE 9
ROR
15:0: BIP error counter lane 9 (NR)
Note: Bits 15:0 are reserved for 40GBASE-R.
0
100
190
BIP ERR
CNT
LANE 10
ROR
15:0: BIP error counter lane 10 (NR)
Note: Bits 15:0 are reserved for 40GBASE-R.
0
101
194
BIP ERR
CNT
LANE 11
ROR
15:0: BIP error counter lane 11 (NR)
Note: Bits 15:0 are reserved for 40GBASE-R.
0
102
198
BIP ERR
CNT
LANE 12
ROR
15:0: BIP error counter lane 12 (NR)
Note: Bits 15:0 are reserved for 40GBASE-R.
0