Figure 15: fifo receive interface, Single frame transfer, Figure 16: fifo receive interface – Achronix Speedster22i 10G/40G/100G Ethernet User Manual
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UG029, September 6, 2013
sys_clk
ff_rx_data[511:0]
ff_rx_sop[0]
ff_rx_eop[0]
ff_rx_mod[5:0]
ff_rx_err[0]
ff_rx_vlan[1:0]
ff_rx_err_stat[23:0]
ff_rx_dval[0]
ff_rx_rdy[0]
ff_rx_preamble_val
ff_rx_preamble[55:0]
Figure 15: FIFO Receive Interface – Single Frame Transfer
A frame transfer is stopped when the internal credit counter reaches 0. When the user
application is able to accept data again, the credit update signal is asserted by the user
application, which increments the internal credit counter. When the credit counter is non-
zero, the MAC Core restarts the data transfer.
sys_clk
ff_rx_data[511:0]
ff_rx_sop[0]
ff_rx_eop[0]
ff_rx_mod[5:0]
ff_rx_err[0]
ff_rx_vlan[1:0]
ff_rx_err_stat[23:0]
ff_rx_dval[0]
ff_rx_rdy[0]
ff_rx_preamble_val
ff_rx_preamble[55:0]
Figure 16: FIFO Receive Interface – Frame Transfer with data valid signal not continuously high