Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 38)

38 UG029, September 6, 2013
sys_clk
ff_tx_wren[0]
ff_tx_data[511:0]
ff_tx_mod[5:0]
ff_tx_sop[0]
ff_tx_eop[0]
ff_tx_err[0]
Figure 12: FIFO Transmit Interface – Frame Transfer with User Application Pause
By keeping the write enable signal (ff_tx_wren[0]) asserted between two consecutive
frames, the user application can send back-to-back frames to the MAC Core.
sys_clk
ff_tx_wren[0]
ff_tx_data[511:0]
ff_tx_mod[5:0]
ff_tx_sop[0]
ff_tx_eop[0]
ff_tx_err[0]
Figure 13: FIFO Transmit Interface – Back-to-Back Frame Transfer
An error from the user application can be reported to the MAC Core by asserting
ff_tx_err[0] at the end of a frame transfer to the FIFO [1]. The frame is then transferred to
the PCS with an Error control code during the frame transfer.
sys_clk
ff_tx_wren[0]
ff_tx_data[511:0]
ff_tx_mod[5:0]
ff_tx_sop[0]
ff_tx_eop[0]
ff_tx_err[0]
Figure 14: FIFO Transmit Interface – Frame Transfer with Error