Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 50)

50 UG029, September 6, 2013
A0,1'b0 A2,A1 A16,A15
sbus_clk
i_sbus_req
i_sbus_data[1:0]
o_sbus_ack
o_sbus_data[1:0] D1,D0 D3,D2 D31,D30 D29,D28
Figure 21: Read in 32-bit Data Bus Mode
A0,1'b0 A2,A1 A16,A15
D1,D0 D3,D2 D7,D6 D5,D4
sbus_clk
i_sbus_req
i_sbus_data[1:0]
o_sbus_ack
o_sbus_data[1:0]
Figure 22: Read in 8-bit Data Bus Mode
Write Operation
For starting a write operation the i_sbus_req is asserted for 25 cycles for the case of a 32-bit
write to the Ethernet SBUS interface or 13 cycles for the case of an 8-bit write to a SerDes
SBUS interface, with the first data bit of i_sbus_d[0] being asserted. The write address which
is 17bit long is sent next with the least significant bit first. The 32-bit or 8-bit write data
follows next.
The SBUS slave decodes the write operation and asserts responds. It then asserts the
o_sbus_ack for 1 cycle on the SBUS interface indicating the completion of write operation.
The figures below shows the timing diagram for a write operation on the SBUS interface.
sbus_clk
i_sbus_req
i_sbus_data[1:0]
o_sbus_ack
A0,1'b1 A2,A1 A16,A15 D1,D0 D3,D2 D31,D30
Figure 23: Write in 32-bit Data Bus Mode
A0,1'b1 A2,A1 A16,A15 D1,D0 D3,D2 D7,D6
sbus_clk
i_sbus_req
i_sbus_data[1:0]
o_sbus_ack
D5,D4
Figure 24: Write in 8-bit Data Bus Mode