beautypg.com
UG029, September 6, 2013
3
Table of Contents
Copyright Info .................................................................................................... 2
Overview ............................................................................................................ 8
Functional Description .................................................................................... 10
Interface Signal List ........................................................................................ 12
Interface Signal Descriptions ......................................................................... 13
Global Signals .............................................................................................................................. 13
Receive FIFO Interface ................................................................................................................ 13
Transmit FIFO Interface ............................................................................................................... 15
PMA TX/RX Interface ................................................................................................................... 16
Priority Flow Control Interface ...................................................................................................... 17
Auto-Negotiation Control and Status ............................................................................................ 18
Serial Bus Interface ...................................................................................................................... 18
SerDes (off-chip) Interface ........................................................................................................... 19
Transmitted Frame Status ............................................................................................................ 19
Timestamp Timer ......................................................................................................................... 19
MAC/PCS Status Indications ........................................................................................................ 20
Implementation with ACE ............................................................................... 21
Software/Hardware Requirements ....................................................................................... 21
Creating an Ethernet Instance ............................................................................................. 21
Configuring the 10/40/100G Ethernet Core .................................................................................. 21
FPGA Fabric Interface ................................................................................................................. 24
PHY Interface ............................................................................................................................... 24
Interface the Ethernet Core to the FPGA Fabric .................................................................. 24
Data ............................................................................................................................................. 24
Serial Bus Interface ...................................................................................................................... 24
Simulation ............................................................................................................................ 24
Clock Distribution ........................................................................................... 26
Reset Considerations ...................................................................................... 28
MAC Soft Reset ................................................................................................................... 28
FIFO / Credit Counter Reset ................................................................................................ 28
PCS Reset ........................................................................................................................... 28
