Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 7)

UG029, September 6, 2013 7
Table of Figures
Figure 1: 10/40/100 Gigabit Ethernet MAC Block Diagram ...................................................... 10
Figure 2: Interface Signal List .................................................................................................. 12
Figure 3: 10/40/100G Ethernet MAC IP Wizard ....................................................................... 22
Figure 4: Generate IP Design Files dialog box ........................................................................ 23
Figure 5: Simulation Flow ........................................................................................................ 25
Figure 6: System clock distribution for the 20-Bit SerDes interface ......................................... 26
Figure 7: Example implementation for the FIFO clock and reset multiplexers ......................... 27
Figure 8: Transmit FIFO Interface Block Diagram ................................................................... 30
Figure 9: Receive FIFO Interface Block Diagram .................................................................... 31
Figure 10: Credit based application interface .......................................................................... 32
Figure 11: FIFO Transmit Interface – Single Frame Transfer .................................................. 37
Figure 12: FIFO Transmit Interface
– Frame Transfer with User Application Pause ............... 38
Figure 13: FIFO Transmit Interface – Back-to-Back Frame Transfer ....................................... 38
Figure 14: FIFO Transmit Interface
– Frame Transfer with Error ............................................. 38
Figure 15: FIFO Receive Interface – Single Frame Transfer ................................................... 40
Figure 16: FIFO Receive Interface
– Frame Transfer with data valid signal not continuously
high .................................................................................................................................... 40
Figure 17: FIFO Receive Interface
– Frame Transfer with Error .............................................. 41
Figure 18: FIFO Receive Interface – Frame Transfer with User Pause ................................... 42
Figure 19: FIFO Sections Configuration and Signals ............................................................... 44
Figure 20: FIFO Sections Related Signaling ............................................................................ 44
Figure 21: Read in 32-bit Data Bus Mode................................................................................ 50
Figure 22: Read in 8-bit Data Bus Mode.................................................................................. 50
Figure 23: Write in 32-bit Data Bus Mode ................................................................................ 50
Figure 24: Write in 8-bit Data Bus Mode .................................................................................. 50
Figure 25: Power State Transitioning Diagram ........................................................................ 53
Figure 26: Auto negotiation Use Flow ...................................................................................... 55