Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 82)

82 UG029, September 6, 2013
Table 46 – PCS Register Map – 10G/40G/100GBASE-PCS Registers
Reg#
Add.
(hex)
Register
Name
Type Description Reset
32 80
10/40/100G
BASE-R
STATUS 1
RO
15:13: Reserved
12: Receive link status. 1=Link up, 0=link
down.
11:4: Reserved
3: 10GBASE-R PRBS9 pattern testing ability.
2: 10GBASE-R PRBS31 pattern testing ability.
1: High BER. 1=PCS reporting a high BER.
0: Block lock. 1=PCS locked to received
blocks.
0
33 84
10/40/100G
BASE-R
STATUS 2
ROR
15: Latched block lock. (LL)
14: Latched high BER. (LH)
13:8: BER counter. (NR)
7:0: Errored blocks counter. (NR)
0
34 88
10G BASE-R
SEED A0
RW Bits 15:0 of Test Pattern Seed A 0
35 8C
10G BASE-R
SEED A1
RW Bits 31:16 of Test Pattern Seed A 0
36 90
10G BASE-R
SEED A2
RW Bits 47:32 of Test Pattern Seed A 0
37 94
10G BASE-R
SEED A3
RW
15:10: Reserved. Always 0, writes ignored.
9:0: Bits 57:48 of Test Pattern Seed A
0
38 98
10G BASE-R
SEED B0
RW Bits 15:0 of Test Pattern Seed B 0
39 9C
10G BASE-R
SEED B1
RW Bits 31:16 of Test Pattern Seed B 0
40 A0
10G BASE-R
SEED B2
RW Bits 47:32 of Test Pattern Seed B 0
41 A4
10G BASE-R
SEED B3
RW
15:10: Reserved. Always 0, writes ignored.
9:0: Bits 57:48 of Test Pattern Seed B
0
42 A8
10/40/100G
BASE-R
TEST
CONTROL
RW
15:7: Reserved. Always 0, writes ignored.
6: 10GBASE-R PRBS9 transmit test-pattern
enable.
5: 10GBASE-R PRBS31 receive test-pattern
enable.
4: 10GBASE-R PRBS31 transmit test-pattern
enable.
3: Transmit test-pattern enable.
2: Receive test-pattern enable.
1: Test pattern select. 1=Square wave,
0=pseudo random.
0: Data pattern select. 1=Zeros data pattern,
0=LF data pattern.
Notes:
Bits 1:0 are fixed to 00 for 100GBASE-R and
40GBASE-R.
When bits 3:2 are enabled, test pattern
according to bits 1:0 are generated for
10GBASE-R, or scrambled idle test pattern
are generated for 100GBASE-R and
40GBASE-R.
Bits 6:4 are not available. Always read
s as ‘0’,
writes are ignored.
0