Dell Broadcom NetXtreme Family of Adapters - Manual (Page 159)

User Diagnostics: Broadcom Broadcom NetXtreme BCM57XX User Guide
file:///C|/Users/Nalina_N_S/Documents/NetXtreme/English/dosdiag.htm[9/5/2014 3:32:22 PM]
C5 VPD
The VPD test first saves the contents of the vital product data (VPD) memory before performing the
test. The test then writes 1 of the 5 test data patterns (0xFF, 0xAA, 0x55, increment data, or
decrement data) into VPD memory. By default, an incremental data pattern is used. The test writes
and reads back the data for the entire test range, and then restores the original contents of the
VPD memory.
C6
ASF
Hardware
Reset Test. This test sets the reset bit and polls for self-clearing bits. This test verifies the reset
value of the registers.
Event Mapping Test. This test sets the SMB_ATTN bit. By changing ASF_ATTN_ LOC bits, the test
verifies the mapping bits in TX_CPU or RX_CPU event bits.
Counter Test
Clears WG_TO, HB_TO, PA_TO, PL_TO, RT_TO bits (by setting the bits) and ensures that the
bits clear.
Clears the timestamp counter. Writes a 1 to each of the PL, PA, HB, WG, RT counters. Sets
the TSC_EN bit.
Polls each PA_TO bit and counts up to 50. Checks if the PL_TO bit is set at the end of the
count to 50. Continues to count up to 200. Checks if all other TO bits are set and verifies if
the timestamp counter is incremented.
C7
Expansion
ROM
This test tests the ability to enable, disable, and access the expansion read-only memory (ROM) on
the adapter.
C8 CPU Fetch This test tests the PCU instruction fetch logic 100 times.
Group D: Driver Associated Tests
D1
MAC
Loopback
This test is an internal loopback data transmit/receive test. It initializes the medium access control
(MAC) into an internal loopback mode and transmits 100 packets. The data should be routed back
to the receive channel and received by the receive routine, which verifies the integrity of data. A
100-Mbit/s data rate is used for this test unless Gigabit Ethernet is enabled.
D2
PHY
Loopback
This test is same as the MAC loopback test (D1), except that the data is routed back via a physical
layer device (PHY). A 100-Mbit/s data rate is used for this test unless Gigabit Ethernet is enabled.
D5
MII
Miscellaneous This test tests the autopolling and PHY interrupt capabilities. These are functions of the PHY.
D6 MSI
This test tests the message signal interrupt (MSI) capability of the adapter. Refer to PCI
Specification, version 2.3, for the MSI definition.
Diagnostic Test Messages
/* 0 */ "PASS",
/* 1 */ "Got 0x%08X @ 0x%08X. Expected 0x%08X",
/* 2 */ "Cannot perform task while chip is running",
/* 3 */ "Invalid NIC device",
/* 4 */ "Read -only bit %s got changed after writing zero
at offset 0x%X",
/* 5 */ "Read -only bit %s got changed after writing one
at offset 0x%X",
/* 6 */ "Read/Write bit %s did not get cleared after writing zero
at offset 0x%X",
/* 7 */ "Read/Write bit %s did not get set after writing one
at offset 0x%X",
/* 8 */ "BIST failed",
/* 9 */ "Could not generate interrupt",
/* 10 */ "Aborted by user",
/* 11 */ "TX DMA:Got 0x%08X @ 0x%08X. Expected 0x%08X",
/* 12 */ "Rx DMA:Got 0x%08X @ 0x%08X. Expected 0x%08X",
/* 13 */ "TX DMA failed",
/* 14 */ "Rx DMA failed",
/* 15 */ "Data error, got 0x%08X at 0x%08X, expected 0x%08X",
/* 16 */ "Second read error, got 0x%08X at 0x%08X, expected 0x%08X",
/* 17 */ "Failed writing EEPROM at 0x%04X",
/* 18 */ "Failed reading EEPROM at 0x%04X",
/* 19 */ "EEPROM data error, got 0x08X at 0x04X, expected 0x%08X",
/* 20 */ "Cannot open file %s",
/* 21 */ "Invalid CPU image file %s",
/* 22 */ "Invalid CPU image size %d",
/* 23 */ "Cannot allocate memory",