Rainbow Electronics DS2143Q - Manual (Page 5)

DS2143/DS2143Q
031397 5/40
PIN DESCRIPTION TYPE SYMBOL
30 LI_CLK O Serial Port Clock for the Line Interface. Connects directly to the SCLK
input pin on the line interface. See Sections 12 and 13 for timing details.
31 LI_CS O Serial Port Chip Select for the Line Interface. Connects directly to the CS
input pin on the line interface. See Sections 12 and 13 for timing details.
32
33 RCHBLK
TCHBLK
O Receive/Transmit Channel Block. A user programmable output that can
be forced high or low during any of the 32 E1 channels. Useful for blocking
clocks to a serial UART or LAPD controller in applications where not all E1
h l d h F i l E ISDN PRI Al f l f l
pp
channels are used such as Fractional E1 or ISDN–PRI. Also useful for locat-
ing individual channels in drop–and–insert applications. See Sections 9 and
13 for details.
34 RLOS/LOTC O Receive Loss of Sync/Loss of Transmit Clock. A dual function output.
If TCR2.0=0, then this pin will toggle high when the synchronizer is searching
for the E1 frame and multiframe. If TCR2.0=1, then this pin will toggle high
if the TCLK pin has not toggled for 5
µ
s.
35 INT2 O Receive Alarm Interrupt 2. Flags host controller during conditions defined
in Status Register 2. Active low, open drain output.
36 INT1 O Receive Alarm Interrupt 1. Flags host controller during alarm conditions
defined in Status Register 1. Active low, open drain output.
37 TLCLK O Transmit Link Clock. 4 KHz to 20 KHz demand clock for the TLINK input.
Controlled by TCR2. See Section 13 for timing details.
38 TLINK I Transmit Link Data. If enabled, this pin will be sampled on the falling edge
of TCLK to insert Sa bits. See Section 13 for timing details.
39 TSYNC I/O Transmit Sync. A pulse at this pin will establish either frame or CAS multi-
frame boundaries for the DS2143. Via TCR1.1, the DS2143 can be pro-
grammed to output either a frame or multiframe pulse at this pin. See Section
13 for timing details.
40 VDD – Positive Supply. 5.0 volts.