Rainbow Electronics DS2143Q - Manual (Page 21)

DS2143/DS2143Q
031397 21/40
9.0 CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers
(RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit
Channel Blocking Registers (TCBR1/TCBR2/TCBR3/
TCBR4) control the RCHBLK and TCHBLK pins
respectively. The RCHBLK and TCHCLK pins are user
programmable outputs that can be forced either high or
low during individual channels. These outputs can be
used to block clocks to a USART or LAPD controller in
ISDN–PRI applications. When the appropriate bits are
set to a one, the RCHBLK and TCHCLK pins will be held
high during the entire corresponding channel time. See
the timing in Section 13 for an example.
RCBR1/RCBR2/RCBR3/RCBR4: RECEIVE CHANNEL BLOCKING REGISTERS
(Address=2B to 2E Hex)
(MSB) (LSB)
CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
SYMBOL POSITION NAME AND DESCRIPTION
CH32 RCBR4.7 Receive Channel Blocking Registers.
0 = force the RCHBLK pin to remain low during this channel time
CH1 RCBR1.0 1 = force the RCHBLK pin high during this channel time
TCBR1/TCBR2/TCBR3/TCBR4: TRANSMIT CHANNEL BLOCKING REGISTERS
(Address=22 to 25 Hex)
(MSB) (LSB)
CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
SYMBOL POSITION NAME AND DESCRIPTION
CH32 TCBR4.7 Transmit Channel Blocking Registers.
0 = force the TCHBLK pin to remain low during this channel time
CH1 TCBR1.0 1 = force the TCHBLK pin high during this channel time
RCBR1 (2B)
RCBR2 (2C)
RCBR3 (2D)
RCBR4 (2E)
TCBR1 (22)
TCBR2 (23)
TCBR3 (24)
TCBR4 (25)