Rainbow Electronics DS2143Q - Manual (Page 20)

DS2143/DS2143Q
031397 20/40
Each Transmit Signaling Register (TS1 to TS16) con-
tains the CAS bits for two timeslots that will be inserted
into the outgoing stream if enabled to do so via TCR1.5.
On multiframe boundaries, the DS2143 will load the val-
ues present in the Transmit Signaling Register into an
outgoing signaling shift register that is internal to the
device. The user can utilize the Transmit Multiframe bit
in Status Register 2 (SR2.5) to know when to update the
signaling bits. The bit will be set every 2 ms and the user
has 2 ms to update the TSR’s before the old data will be
retransmitted.
The TS1 register is special because it contains the CAS
multiframe alignment word in its upper nibble. The
upper four bits must always be set to 0000 or else the
terminal at the far end will lose multiframe synchroniza-
tion. If the user wishes to transmit a multiframe alarm to
the far end, then the TS1.2 bit should be set to a one. If
no alarm is to be transmitted, then the TS1.2 bit should
be cleared. The three remaining bits in TS1 are the
spare bits. If they are not used, they should be set to
one. In CCS signaling mode, TS1 to TS16 can also be
used to insert signaling information. Via the SR2.5 bit,
the user will be informed when the signaling register s
need to be loaded with data. The user has 2 ms to load
the data before the old data will be retransmitted.
8.0 TRANSMIT IDLE REGISTERS
There is a set of five registers in the DS2143 that can be
used to custom tailor the data that is to be transmitted
onto the E1 line, on a channel by channel basis. Each of
the 32 E1 channels can be forced to have a user defined
idle code inserted into them.
TIR1/TIR2/TIR3/TIR4: TRANSMIT IDLE REGISTERS (Address=26 to 29 Hex)
(MSB) (LSB)
CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
SYMBOL POSITION NAME AND DESCRIPTION
CH32 TIR4.7 Transmit Idle Registers.
0 = do not insert the Idle Code into this channel
CH1 TIR1.0 1 = insert the Idle Code into this channel
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=2A Hex)
(MSB) (LSB)
TIDR7 TIDR6 TIDR5 TIDR4 TIDR3 TIDR2 TIDR1 TIDR0
SYMBOL POSITION NAME AND DESCRIPTION
TIDR7 TIDR.7 MSB of the Idle Code
TIDR0 TIDR.0 LSB of the Idle Code
Each of the bit positons in the Transmit Idle Registers
(TIR1/TIR2/TIR3/TIR4) represent a timeslot in the out-
going frame. When these bits are set to a one, the corre- sponding channel will transmit the Idle Code contained
in the Transmit Idle Definition Register (TIDR). In the
TIDR, the MSB is transmitted first.
TIR1 (26)
TIR2 (27)
TIR3 (28)
TIR4 (29)