Rainbow Electronics DS2143Q - Manual (Page 22)

DS2143/DS2143Q
031397 22/40
10.0 ELASTIC STORE OPERATION
The DS2143 has an onboard two frame (512 bits) elas-
tic store. This elastic store can be enabled via RCR2.1.
If the elastic store is enabled (RCR2.1=1), then the user
must provide either a 1.544 MHz (RCR2.2=0) or 2.048
MHz (RCR2.2=1) clock at the SYSCLK pin. If the elastic
store is enabled, then the user has the option of either
providing a frame sync at the RFSYNC pin (RCR1.5=1)
or having the RFSYNC pin provide a pulse on frame or
multiframe boundaries (RCR1.5=0). If the user wishes
to obtain pulses at the frame boundary, then RCR1.6
must be set to zero and if the user wishes to have pulses
occur at the multiframe boundary, then RCR1.6 must be
set to one. If the user selects to apply a 1.544 MHz clock
to the SYSCLK pin, then every fourth channel will be
deleted and the F–bit position inserted (forced to one).
Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots
0, 4 , 8, 12, 16, 20, 24, and 28) will be deleted. Also, in
1.544 MHz applications, the RCHBLK output will not be
active in channels 25 through 32 (or in other words,
RCBR4 is not active). See Section 13 for more details.
If the 512–bit elastic buffer either fills or empties, a con-
trolled slip will occur. If the buffer empties, then a full
frame of data (256 bits) will be repeated at RSER and
the SR1.4 and RIR.3 bits will be set to a one. If the buffer
fills, then a full frame of data will be deleted and the
SR1.4 and RIR.4 bits will be set to a one.
11.0 ADDITIONAL (Sa) AND
INTERNATIONAL (Si) BIT OPERATION
The DS2143 provides for access to both the Additional
(Sa) and International (Si) bits. On the receive side, the
RAF and RNAF registers will always report the data as it
received in the Additional and International bit locations.
The RAF and RNAF registers are updated with the set-
ting of the Receive Align Frame bit in Status Register 2
(SR2.6). The host can use the SR2.6 bit to know when
to read the RAF and RNAF registers. It has 250
µ s to
retrieve the data before it is lost.
On the transmit side, data is sampled from the TAF and
TNAF registers with the setting of the Transmit Align
Frame bit in Status Register 2 (SR2.3). The host can
use the SR2.3 bit to know when to update the TAF and
TNAF registers. It has 250
µ
s to update the data or else
the old data will be retransmitted. Data in the Si bit posi-
tion will be overwritten if either the DS2143 is pro-
grammed: (1) to source the Si bits from the TSER pin,
(2) in the CRC4 mode, or (3) have automatic E–bit inser-
tion enabled. Data in the Sa bit position will be overwrit-
ten if any of the TCR2.3 to TCR2.7 bits are set to one.
Please see the register descriptions for TCR1 and
TCR2 and the Transmit Data Flow diagram in Section
13 for more details.
RAF: RECEIVE ALIGN FRAME REGISTER (Address=2F Hex)
(MSB) (LSB)
Si 0 0 1 1 0 1 1
SYMBOL POSITION NAME AND DESCRIPTION
Si RAF.7 International Bit.
0 RAF.6 Frame Alignment Signal Bit.
0 RAF.5 Frame Alignment Signal Bit.
1 RAF.4 Frame Alignment Signal Bit.
1 RAF.3 Frame Alignment Signal Bit.
0 RAF.2 Frame Alignment Signal Bit.
1 RAF.1 Frame Alignment Signal Bit.
1 RAF.0 Frame Alignment Signal Bit.