Rainbow Electronics DS2143Q - Manual (Page 17)

DS2143/DS2143Q
031397 17/40
BPVCR1: UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address=00 Hex)
BPVCR2: LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address=01 Hex)
(MSB) (LSB)
BV7 BV6 BV5 BV4 BV3 BV2 BV1 BV0
BV15 BV14 BV13 BV12 BV11 BV10 BV9 BV8
SYMBOL POSITION NAME AND DESCRIPTION
BV15 BPVCR1.7 MSB of the bipolar violation count
BV0 BPVCR2.0 LSB of the bipolar violation count
Bipolar Violation Count Register 1 (BPVCR1) is the
most significant word and BPVCR2 is the least signifi-
cant word of a 16–bit counter that records bipolar viola-
tions (BPVs). If the HDB3 mode is set for the receive
side via CCR.2, then HDB3 code words are not counted. This counter increments at all times and is not disabled
by loss of sync conditions. The counter saturates at
65,535 and will not rollover. The bit error rate on a E1
line would have to be greater than 10**–2 before the
BPVCR would saturate.
CRCCR1: CRC4 COUNT REGISTER 1 (Address=02 Hex)
CRCCR2: CRC4 COUNT REGISTER 2 (Address=03 Hex)
(MSB) (LSB)
CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0
CRC14 CRC14 CRC13 CRC12 CRC11 CRC10 CRC9 CRC8
SYMBOL POSITION NAME AND DESCRIPTION
CRC15 CRCCR1.7 MSB of the CRC4 error count
CRC0 CRCCR2.0 LSB of the CRC4 error count
CRC4 Count Register 1 (CRCCR1) is the most signifi-
cant word and CRCCR2 is the least significant word of a
16–bit counter that records word errors in the Cyclic
Redundancy Check 4 (CRC4). Since the maximum CRC4 count in a one second period is 1000, this counter
cannot saturate. The counter is disabled during loss of
sync at either the FAS or CRC4 level; it will continue to
count if loss of sync occurs at the CAS level.
EBCR1: E–BIT COUNT REGISTER 1 (Address=04 Hex)
EBCR2: E–BIT COUNT REGISTER 2 (Address=05 Hex)
(MSB) (LSB)
EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
EB15 EB14 EB13 EB12 EB11 EB10 EB9 EB8
SYMBOL POSITION NAME AND DESCRIPTION
EB15 EBCR1.7 MSB of the E–Bit error count
EB0 EBCR2.0 LSB of the E–Bit error count
E–bit Count Register 1 (EBCR1) is the most significant
word and EBCR2 is the least significant word of a 16–bit
counter that records Far End Block Errors (FEBE) as
reported in the first bit of frames 13 and 15 on E1 lines
running with CRC4 multiframe. These count registers will increment once each time the received E–bit is set to
zero. Since the maximum E–bit count in a one second
period is 1000, this counter cannot saturate. The
counter is disabled during loss of sync at either the FAS
BPVCR2
BPVCR1
CRCCR2
CRCCR1
EBCR2
EBCR1