Rainbow Electronics DS2141A - Manual (Page 26)

DS2141A
021997 26/35
TRANSMIT SIDE ESF TIMING
FRAME#
TSYNC 1
TSYNC 2
TSYNC 3
TLCLK 4
TLINK 5
TLCLK 6
TLINK 7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
NOTES:
1. TSYNC in the frame mode (TCR2.3=0) and double–wide frame sync is not enabled (TCR2.4=0).
2. TSYNC in the frame mode (TCR2.3=0) and double–wide frame sync is enabled (TCR2.4=1).
3. TSYNC in the multiframe mode (TCR2.4=1).
4. ZBTSI mode disabled (TCR2.5=0).
5. TLINK data (FDL bits) is sampled during the F–bit time of odd frame and inserted into the outgoing T1 stream if
enabled via TCR1.2.
6. ZBTSI mode is enabled (TCR2.5=1).
7. TLINK data (Z bits) is sampled during the F–bit time of frame 1, 5, 9, 13, 17, and 21 and inserted into the outgoing
stream if enabled via TCR1.2.