Rainbow Electronics DS2141A - Manual (Page 25)

DS2141A
021997 25/35
RECEIVE SIDE BOUNDARY TIMING (WITH ELASTIC STORE(S) DISABLED)
RCLK
RPOS 1 ,
RNEG
TSER/
RSER
1
RSYNC
RCHCLK
RCHBLK 2
RLCLK
RLINK
LSB F MSB LSB MSB LSB MSB
CHANNEL 1 CHANNEL 2
LSB MSB LSB MSB F
CHANNEL 23 CHANNEL 24 CHANNEL 1
NOTES:
1. There is a 13 RCLK delay from RPOS, RNEG to RSER.
2. RCHBLK is programmed to block Channel 24.
TRANSMIT SIDE D4 TIMING
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 FRAME#
TSYNC 1
TSYNC 2
TSYNC 3
TLCLK
TLINK 4
NOTES:
1. TSYNC in the frame mode (TCR2.3=0) and double–wide frame sync is not enabled (TCR2.4=0).
2. TSYNC in the frame mode (TCR2.3=0) and double–wide frame sync is enabled (TCR2.4=1).
3. TSYNC in the multiframe mode (TCR2.3=1).
4. TLINK data (S–bit) is sampled during the F–bit position of even frames for insertion into the outgoing T1 stream
when enabled via TCR1.2.