Rainbow Electronics DS2141A User Manual

Page 19

DS2141A

021997 19/35

Each Receive Signaling Register (RS1 to RS12) reports
the incoming robbed bit signaling from eight DS0 chan-
nels. In the ESF framing mode, there can be up to four
signaling bits per channel (A, B, C, and D). In the D4
framing mode, there are only two framing bits per chan-
nel (A and B). In the D4 framing mode, the DS2141A will
replace the C and D signaling bit positions with the A and
B signaling bits from the previous multiframe. Hence,
whether the DS2141A is operated in either framing

mode, the user needs only to retrieve the signaling bits
every 3 ms. The bits in the Receive Signaling Registers
are updated on multiframe boundaries so the user can
utilize the Receive Multiframe Interrupt in the Receive
Status Register 2 (SR2.7) to know when to retrieve the
signaling bits. The Receive Signaling Registers are fro-
zen and not updated during a loss of sync condition
(SR1.0=1). They will contain the most recent signaling
information before the “OOF” occurred.

TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (70h to 7Bh)

(MSB)

(LSB)

A(8)

A(7)

A(6)

A(5)

A(4)

A(3)

A(2)

A(1)

A(16)

A(15)

A(14)

A(13)

A(12)

A(11)

A(10)

A(9)

A(24)

A(23)

A(22)

A(21)

A(20)

A(19)

A(18)

A(17)

B(8)

B(7)

B(6)

B(5)

B(4)

B(3)

B(2)

B(1)

B(16)

B(15)

B(14)

B(13)

B(12)

B(11)

B(10)

B(9)

B(24)

B(23)

B(22)

B(21)

B(20)

B(19)

B(18)

B(17)

C(8)

C(7)

C(6)

C(5)

C(4)

C(3)

C(2)

C(1)

C(16)

C(15)

C(14)

C(13)

C(12)

C(11)

C(10)

C(9)

C(24)

C(23)

C(22)

C(21)

C(20)

C(19)

C(18)

C(17)

D(8)

D(7)

D(6)

D(5)

D(4)

D(3)

D(2)

D(1)

D(16)

D(15)

D(14)

D(13)

D(12)

D(11)

D(10)

D(9)

D(24)

D(23)

D(22)

D(21)

D(20)

D(19)

D(18)

D(17)

SYMBOL

POSITION

NAME AND DESCRIPTION

D(24)

TS12.7

Signaling Bit D in Channel 24.

A(1)

TS1.0

Signaling Bit A in Channel 1.

Each Transmit Signaling Register (TS1 to TS12) con-
tains the Robbed Bit signaling for eight DS0 channels
that will be inserted into the outgoing stream if enabled
to do so via TCR1.4. In the ESF framing mode, there
can be up to four signaling bits per channel (A, B, C, and
D). In the D4 framing mode, there are only two framing
bits per channel (A and B). On multiframe boundaries,
the DS2141A will load the values present in the Trans-
mit Signaling Register into an outgoing signaling shift
register that is internal to the device. The user can uti-
lize the Transmit Multiframe Interrupt in Status Register
2 (SR2.6) to know when to update the signaling bits.

8.0 SPECIAL TRANSMIT SIDE REGISTERS

There is a set of seven registers in the DS2141A that
can be used to custom tailor the data that is to be trans-
mitted onto the T1 line, on a channel by channel basis.
Each of the 24 T1 channels can be either forced to be
transparent or to have a user defined idle code inserted
into them. Each of these special registers is defined be-
low.

TS1 (70)

TS2 (71)

TS3 (71)

TS4 (73)

TS5 (74)

TS6 (75)

TS7 (76)

TS8 (77)

TS9 (78)

TS10 (79)

TS11 (7A)

TS12 (7B)